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pixels network show mybox
，这一点在服务器推荐中也有详细论述
When VM=1, the protected-mode bit goes low and the Entry PLA selects real-mode entry points -- MOV ES, reg takes the one-line path. Meanwhile, CPL is hardwired to 3 whenever VM=1, so the V86 task always runs at the lowest privilege level, under full paging protection. The OS can use paging to virtualize the 8086's 1 MB address space, even simulating A20 address line wraparound by mapping pages to the same physical frames.
// Even if the readable side's buffer is full, this succeeds
"Full of little nooks and crannies where they can roost, big open flight spaces, dry spaces inside, away from the rain, where they can fly around. It is really just an absolutely perfect environment."